1. Field of the Invention
The present invention generally relates to a non-volatile semiconductor memory, and in particular to a control method for a non-volatile memory including a floating gate.
2. Description of the Related Art
In a flash memory cell array where the cell data stored in a plurality of selected cells can be erased concurrently, the cell data are usually erased with Fowler-Nordheim (F-N) tunneling currents to emit the electrons stored in the floating gate to the source or the substrate. However, there is distribution of the F-N tunneling current caused by distribution of physical parameters such as the thickness of gate insulation film and the overlapped area of the source and the floating gate among memory cells. The distribution of the F-N tunneling current causes the distribution of the erased cell threshold voltage (erased-V.sub.TM).
To suppress this erased-V.sub.TM distribution, there has been proposed the 2-step erasing method in the article "A Novel Erasing Technology for 3.3 V Flash Memory with 64 Mb Capacity and Beyond" written by Okazawa et al. (IEEE International Electron Device Meeting (IEDM) 92, pp. 607-610, 1992) and Japanese Patent Unexamined Publication No. 5-258583. The 2-step erasing method consists of two different cell gate bias conditions. In the IEDM a first document step, a negative high voltage is applied to the control gates of the cells to erase the cell data, and in a second step, a positive high voltage is applied to decrease the erased-V.sub.TM distribution (see FIG. 6). According to a control method disclosed in the Publication (5-258583), in the first step, a negative high voltage is applied to the control gates of the cells and, at the same time, a positive voltage is applied to the source to erase the cell data.